A new active neutral point clamped (ANPC) nine-level inverter topology with low energy storage switched capacitors | Scientific Reports

Scientific Reports volume 15, Article number: 7031 (2025) Cite this article

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The ANPC-based multilevel inverters have been quite famous for over a decade due to their lower devices and high efficiency. However, as the number of levels increases, the ANPC topologies become unsuitable due to the increase in the component count and capacitor voltage balancing issue. This article proposes a novel ANPC nine-level topology with reduced components and voltage stress on the components. The proposed circuit has eight switches and one bidirectional switch, with two switched capacitors. The proposed topology has the voltage boosting ability with a maximum voltage gain of two times that of the conventional ANPC topologies. Further, the proposed topology does not need any voltage-balancing algorithm to maintain the SC voltages. The proposed topology is validated in hardware, and results are presented. The maximum voltage is 200 V, and the maximum current is 2.4 A with a maximum efficiency of 97% 100 W.

Multilevel inverters (MLIs) are predominated and well-matured power converters ideal for medium—and high-voltage applications such as high-power AC drives, flexible AC transmission systems (FACTS), high-voltage direct current (HVDC) transmission, and large-scale renewable energy systems (RESs)1,2. In contrast to conventional two-level inverters, MLIs provide a range of significant advantages. They substantially reduce voltage stress on power devices, enhancing these components’ reliability and operational lifespan and improving overall system performance. Additionally, MLIs effectively minimize electromagnetic interference (EMI), ensuring cleaner signals and reducing noise in sensitive applications. Moreover, MLIs achieve lower total harmonic distortion (THD), resulting in a higher-quality output waveform, thus improving power delivery efficiency. They also help reduce the common-mode voltage, which is crucial for preventing potential issues related to system stability and equipment protection3,4. These features make MLIs particularly advantageous in modern electrical systems, where the demand for efficiency, power quality (PQ), and robust performance is increasingly critical. Their ability to manage higher voltage levels with fewer components contributes to cost-effectiveness. It supports the advancement of power electronics technology, positioning MLIs as key players in the future of energy systems.

The first cascaded H-bridge multilevel inverter (MLI) was introduced in 1975 and developed by Baker et al. This pioneering work laid the foundation for subsequent advancements in the field. Two additional MLI topologies—the neutral point clamped (NPC) and flying capacitor (FC) configurations—were introduced the following year, marking significant milestones in power electronics and power system-based power electronic applications.

While conventional MLI topologies are recognized for their excellent modularity and reduced voltage stress on switches, they inherently require many components. These include switches, clamping diodes, isolated DC sources, and DC-link capacitors5. The increased component count leads to higher costs and larger system sizes and weights, posing challenges in practical applications. Innovative hybrid multilevel inverters have been developed to mitigate these drawbacks without compromising the advantageous features of traditional MLIs. These hybrids effectively combine elements from both conventional and contemporary topologies, emerging as viable solutions to the limitations inherent in earlier designs. Among these, the active neutral point clamped (ANPC), and FC hybrid topologies have garnered significant attention within the research community. However, it is important to note that these hybrid topologies often rely on complex algorithms for managing FC voltages. This requirement burdens digital controllers and increases costs due to the need for supplementary sensors. As a result, while these advancements present promising alternatives, they also introduce new challenges that must be addressed to fully leverage their potential in practical applications.

Recently, switched-capacitor multilevel inverter (SCMLI) topologies have emerged as a transformative solution for generating desired output voltages, effectively utilizing single or multiple isolated DC sources. Researchers have reported a variety of configurations that enhance performance, with SCMLIs spanning from three-level (3 L) to nineteen-level (19 L) designs, as highlighted in6. Nine-level SCMLI topologies have gained considerable attention in the literature7,8,9,10,11,12,13,14,15,16.

One notable advancement is the introduction of the FC-based nine-level (9 L) inverter topology, which features reduced inrush current and operates without the need for a sensor, as presented in7. This design employs gate logic to maintain the voltage across the flying capacitors; however, it lacks the capability for voltage boosting, which limits its versatility. Further innovations have been proposed, such as a 9 L inverter topology that operates at both fundamental and high switching frequencies to minimize power losses and achieve effective voltage balancing across the switched capacitors8. A nine-level double hybrid active NPC topology introduced in9 also employs digital logic functions and voltage sensors for capacitor voltage balancing. Nevertheless, these designs often face a significant limitation: the output voltage is constrained to match the input voltage, thereby restricting their range of applications.

To address these challenges, researchers have developed SCMLIs with enhanced boosting capabilities9,10,11,12,13,14,15,16. These advancements not only expand the operational range of the inverters but also improve their applicability in various high-performance scenarios, paving the way for more efficient and adaptable power conversion solutions.

In9, a novel ANPC-based nine-level inverter is introduced, characterized by a reduced device count of ten switches and four diodes. However, this topology does not include an inrush current limiter, which may lead to potential challenges during operation. Furthermore, the sizing of power components and the energy storage requirements for the capacitors are not addressed, leaving gaps in the design considerations. Additionally, nine-level boost converters are discussed in10,11, which offer self-voltage balancing capabilities with an impressive output voltage that can reach four times higher than the input voltage (Vdc). Despite these advantages, such topologies are not ideal for high-voltage applications, as they necessitate capacitors and switches rated for higher voltages, thus complicating their implementation.

Several compact topologies that enhance self-voltage balancing and boosting capabilities are proposed in12,13,14. These designs successfully reduce the number of components while lowering the switch’s blocking voltage requirements. Notably, the voltage rating of the switched capacitors is set to half of Vdc in12,13, while14 presents a case where it equals Vdc. Furthermore, topologies discussed in15,16 showcase a nine-level ANPC configuration with a reduced device count; however, these designs increase the number of switched capacitors to three. While the topology achieves a voltage gain of two times that of the input, the switch voltages remain equal to the input voltage. In general, despite these advancements, many of these designs are not fully optimized for minimizing power component requirements, alleviating voltage stress on switches, or addressing capacitor voltage ratings. Consequently, several topologies17,18,19,20,21,22 continue to encounter challenges when applied in high-voltage scenarios, highlighting the need for further refinement and innovation in MLIs. Further, the modulation techniques are responsible for the quality of the output voltage and current, which is associated with power losses. The modulation schemes are basically classified into two types based on the switching frequency. Those are (i) fundamental switching frequency modulation schemes such as nearest level modulation scheme (NLC)23 and improved NLC24, which has low DC losses, selective harmonics elimination (SHE)25 methods which explain the third harmonics elimination method for high-frequency power distribution system application, and (ii) high switching frequency, phase disposition (PD), phase opposition disposition (POD), alternate phase opposition disposition (APOD), pseudorandom carrier modulation scheme, and others26 which produce the random carrier signal with support of the random bit generator i.e. not fixed frequency and multiplexer. This pseudorandom method produces low-voltage THD as compared to the fixed modulation method. Another modulation method is the single carrier scheme presented in27, where the number of carrier signals is reduced, but the reference sinusoidal waveform increases. However, the proposed scheme also produces better THD than existing modulation schemes. The novel “un” shaped carrier signal is introduced in28. The proposed modulation scheme was tested for higher voltage levels and was proved to have low THD compared to the existing modulation scheme. However, the generation of carrier signals is a little more difficult than the existing one.

In this regard, this paper introduces an innovative SCMLI topology that utilizes components with low voltage ratings to address these limitations. This novel design significantly enhances the overall efficiency and practicality of MLI-based systems. The key advantages of the proposed topology are:

Reduced DC-link voltage requirement: Unlike conventional mid-point clamped topologies, which necessitate a higher DC-link voltage, our proposed topology effectively halves this requirement, leading to a more efficient design.

Elimination of complex control needs: The topology removes the dependency on voltage-balancing sensors and intricate control algorithms, simplifying the overall system architecture and reducing potential points of failure.

Enhanced efficiency and cost reduction: By minimizing the number of components, our design boosts efficiency and lowers overall production costs, making it a more economically viable option for implementation.

Improved system performance: Integrating low-energy storage SCs further optimizes system performance, contributing to better energy management and reduced operational losses.

The structure of this paper is outlined as follows:

Section 2: Provides a detailed description of the proposed topology and its various modes of operation.

Section 3: Discusses the conventional pulse-width modulation (PWM) technique and the design considerations for passive components, including an inrush current limiter.

Section 4: Presents a comparison of proposed MLI with other recent MLI topologies.

Section 5: Presents comprehensive simulation and experimental results for the nine-level output under varying load and input conditions, showcasing the effectiveness of the proposed topology.

Section 6: Concludes with a summary of the topology’s advantages and potential implications for future applications in power electronics.

Figure 1 illustrates the circuit diagram of the proposed nine-level inverter, which features a reduced device count and optimized voltage ratings for its components. This innovative topology comprises eight unidirectional switches (S₁-S₂ and S₅-S₈) and two bidirectional switches (S₃-S₄ and S₉-S₁₀), facilitating efficient operation.

Proposed 9 L inverter topology circuit diagram.

The design utilizes two DC sources, each rated at Vdc/2, which can be substituted with a single DC source paired with two capacitors, allowing for the equation Vdc=Vdc1+Vdc2​. This configuration is reminiscent of the conventional ANPC-3 L inverter structure. Additionally, the circuit incorporates four diodes (D₁-D₄) to enhance functionality and reliability. Notably, two switched capacitors (SC₁ and SC₂) are included, each rated at half the voltage of the DC-link capacitor (Vdc/4), thus optimizing energy storage while minimizing voltage stress. The load is connected between switches S₇ and S₈, effectively linking it to the midpoint of the two DC sources, Vdc1 and Vdc2. Furthermore, switches S₅ and S₆ are cross-connected to facilitate the addition of the switched capacitor voltages, enhancing the inverter’s output flexibility. This designed topology improves efficiency and simplifies the overall structure, making it a compelling solution for modern power conversion applications. Figure 2 (a)-(i) illustrates the various modes of operation of the proposed topology, clearly showcasing the multiple current paths utilized to achieve the desired output voltage levels. Each mode ensures that reactive power flows smoothly without disruption, enhancing the system’s overall stability. During the charging process of the SCs, inrush or impulsive currents may occur. To effectively mitigate these inrush currents, it is advisable to incorporate an inductor or other current-limiting components within the capacitor charging path. This addition helps to soften the initial surge of current, protecting the circuit components and ensuring optimal performance. The depiction of these operational modes provides insight into the proposed topology’s functionality and underscores the design considerations that enhance its reliability and efficiency in practical applications. This topology demonstrates significant advancements in MLI technology by carefully managing current paths and addressing inrush currents.

In Mode 0 (+ 0Vdc), the system achieves an initial voltage level of zero volts by subtracting the precharged SCs from DC source Vdc1. Concurrently, the switched capacitors (SC₁ and SC₂) are charged to a voltage of Vdc/4, as depicted in Fig. 2a. The operational path for this mode is defined by the sequence of switches and diodes: S₁, D₃, D₄, S₃, and S₄. The switch and current paths are given in Table 1. This configuration allows for efficient current flow while ensuring the voltage remains zero, setting the stage for subsequent operational modes. This arrangement highlights the functionality of the proposed topology and emphasizes the strategic management of voltage levels within the inverter. By controlling the charging of the switched capacitors and utilizing specific current paths, the system maintains stability and readiness for further voltage transitions.

Modes of operation of the proposed topology: (a) zeroth State, (b–e) positive cycle, and (f–i) negative cycle.

In Mode 1, the inverter achieves a voltage level of + Vdc/4. During this phase, the switched capacitors SC₁ and SC₂ charge through the pathway defined by the switches S₁, D₃, D₄, D₂, S₃, and S₄. This configuration allows efficient energy transfer to the capacitors while simultaneously enabling switches S₉ and S₁₀ to deliver + Vdc/4 to the load. This dual operation facilitates capacitor charging and establishes the first incremental voltage level in the output. Transitioning to Mode 2, the current path to the load shifts to S₁, D₃, and S₇, which generates an output voltage of + Vdc/2. At the same time, the switched capacitors SC₁ and SC₂ continue to charge to + Vdc/4 through the path D₄, D₂, S₃, and S₄. This continuous charging of the capacitors in the first three modes represents a significant advantage of the proposed topology, ensuring that energy storage is consistently optimized. In Mode 3, the current flows through S₁, S₅, S₉, and S₁₀, with the switched capacitor SC₂ actively charging while SC₃ remains idle—neither charging nor discharging. This strategic arrangement allows for effective energy management within the system. As the system progresses to Mode 4, both switched capacitors SC₁ and SC₂ discharge through S₁, S₅, and S₇. Notably, across the nine operational levels, the switched capacitors discharge during three levels and remain idle during one level, with the remaining five levels devoted to capacitor charging. The voltages across the switched capacitors can be represented as:

where VSC1, and VSC2 are the voltages across the SCs. Meanwhile, the voltage across the DC-link capacitor (or DC source) is given by:

In this context, the switching function’s logic values are denoted as {1,0}, where “1” signifies the ON state and “0” denotes the OFF state. The precise activation and deactivation of the switches correspond to the sequence outlined in Table 1, ensuring smooth transitions between operational modes. This well-coordinated switching strategy enhances the overall reliability and efficiency of the proposed topology, making it a robust solution for MLI applications.

Figure 3a,b presents a comparative analysis of conventional triangular carrier signals versus improved carrier signals, as discussed in15, highlighting the effects of varying the parameter “dx.” When the value of dx ranges between 0 and 1, its impact on the switching dynamics becomes evident. At lower dx values, such as 0.1, the potential for extending the switching period is limited. Conversely, as the dx value increases, particularly beyond 0.5, the number of switching periods can double; however, this also reduces the width of each switching period. The improved carrier signal facilitates more switching points than the conventional triangular signal, directly enhancing the output voltage’s total harmonic distortion (THD) profile. While both conventional and improved carrier signals operate at the same switching frequency, the proposed signal achieves a higher root mean square (RMS) voltage. It exhibits improved THD due to the increased number of switching periods. A detailed analysis of this enhanced carrier signal can be found in15, emphasizing its capability to minimize THD further. Therefore, selecting an optimal dx value that is greater than 0.5 is essential for maximizing performance. The proposed improved level-shifted (LS) multicarrier PWM signal, along with its reference waveform, is illustrated in Fig. 3b, showcasing the advantages of this approach in enhancing voltage quality and reducing harmonic distortion. This innovative strategy represents a significant advancement in multilevel inverter technology, paving the way for more efficient and reliable power conversion systems.

Improved triangular carrier signal: (a) conventional triangular and improved triangular carrier signal and (b) improved LS multicarrier PWM signal.

Consider a function f(x, y) for a two-level full bridge inverter is16:

The above equation encompasses both the fundamental and harmonic components, with q and p representing the carrier and baseband index variables, respectively15.

In the context of the proposed topology, which generates a double pulse when dx ≠ 1, the Fourier series representation can be streamlined to reflect this behavior more accurately. Specifically, the simplification allows for a clearer analysis of the signal’s frequency components, focusing on how the modulation impacts the overall waveform.

The proposed modulation scheme’s duty ratio exceeds that of LSPWM, resulting in reduced conduction time. This characteristic is advantageous, as it allows for more efficient inverter operation. Additionally, the switching angles of each pulse in the proposed modulation technique differ significantly from those in conventional PWM, contributing to a notable reduction in THD, as depicted in Fig. 3. Figure 3b showcases the level-shifted carrier signals (VCar1-VCar4) used for both positive and negative cycles alongside a sinusoidal reference signal (VRef). The elevated duty ratio of the proposed modulation scheme facilitates extended conduction times compared to traditional PWM methods. This results in distinct differences in switching periods and pulse widths, optimizing the inverter’s performance. The innovative approach enhances the quality of the output voltage and improves the overall efficiency of the system. By carefully managing the duty ratios and pulse characteristics, the proposed modulation scheme minimizes harmonic distortion while maximizing the inverter’s operational capabilities.

A straightforward lookup table generates the gating pulses, facilitating efficient control of the inverter’s operation. The modulation index D is mathematically defined as \(\:D=\frac{{V}_{ref}}{{4\,V}_{dc}}\), where Vref represents the maximum amplitude of the reference sinusoidal signal, and Vdc​ denotes the peak value of the carrier signal. This definition is crucial for understanding the relationship between the reference signal and the inverter’s output. Figure 4 graphically represents the level switching angles, which are critical for determining the timing of the gating pulses.

Typical 9 L inverter output voltage waveform with high switching frequency.

These angles shape the output waveform, allowing precise control over the inverter’s voltage levels. These level switching angle formulations are given in (5).

The proposed topology ensures optimal performance while minimizing THD by employing this modulation index and the corresponding switching angles. This pulse generation method enhances the output voltage’s accuracy and improves the system’s overall efficiency. As discussed above, it is important to compare the proposed carrier signal-based modulation technique with an existing conventional carrier signal. Any modulation scheme’s outcome directly impacts the THD and voltage root mean square (RMS) value. A detailed comparison of conventional sawtooth and various conventional triangular modulation schemes based on simulation results is given in Table 2.

The selection of SCs29 is important to allow a percentage of ripple, which provides the output voltage quality. The SCs are parallel to the Vdc1/2 during the ± Vdc/2, ±Vdc/4, and zero voltage levels.

To simplify the analysis of self-balancing, D = 1, where duty cycle variation in the areas A1–A4 over the half cycle is explained as follows:

First area (A1): The level ± Vdc/4 is generated by charging \(\:{\text{S}\text{C}}_{1}\) from \(\:{C}_{1}\) (i.e., \(\:{V}_{dc1}-{V}_{\text{S}\text{C}1}\)). Therefore, the total charge (\(\:{TQ}_{{A}_{1}}\)) supplied to the load \(\:\left({Z}_{L}={R}_{L}+j{L}_{L}\right)\) is expressed as follows:

Second area \(\:\left({A}_{2}\right)\) : In this area, the output voltage toggles between ± Vdc/4 and ± Vdc/2 levels. The duty cycles corresponding to these levels over \(\:{T}_{Sw}\) are expressed as:

Here, level ± Vdc/2 is equal to \(\:{V}_{dc1}\) voltage and level ± Vdc/4 is the same voltage as \(\:\left({V}_{dc1}-{V}_{\text{S}\text{C}1}\right)\). Therefore, \(\:{TQ}_{{A}_{2}}\) supplied to \(\:{R}_{L}+j{L}_{L}\)is obtained as follows:

Similarly, for areas A3 & A4, relations are obtained as follows:

From (4), (6), (8), (10), and (11), the average current flowing through the neutral point over the fundamental period is expressed as:

During steady-state operation, the average current through the neutral point must remain zero. This condition ensures balanced operation and prevents voltage drift in the system. To accurately estimate the required capacitance values, it is crucial to consider the longest discharging period of the capacitors involved. The capacitances of \(\:{SC}_{1}\) & \(\:{SC}_{2}\) are obtained by considering that \(\:+{V}_{dc}\) (i.e., SC2 is discharging long levels) and \(\:-{V}_{dc}\) (i.e., SC1 is discharging long levels) have their longest discharging period, respectively; thus:

The optimal selection for ripple voltage (\(\:{\Delta\:}{V}_{Rip}\)​) is typically maintained within 5%. This threshold ensures performance and stability in the inverter’s operation. However, in addition to determining the appropriate capacitor sizing, it is crucial to select a suitable value for the inrush limiting inductor (\(\:{L}_{ir}\))30. This inductor plays a vital role in suppressing the impulse charging current during periodic intervals when the capacitors are charged. The inrush-limiting inductor mitigates the initial surge of current, protecting the circuit components from potential damage and ensuring smooth operation during startup conditions. By carefully sizing the inductor, the inrush current can be effectively controlled while maintaining the desired ripple voltage levels. Thus:

where \(\:{\Delta\:}V\) is the maximum voltage difference between Vdc1−2 /dc-link voltage and SC.

From (19), the maximum value of the inductor current (\(\:{i}_{{L}_{ir}\text{m}\text{a}\text{x}}\)) is further derived and is given as follows:

where \(\:\phi\:={\text{t}\text{a}\text{n}}^{-1}\left(2{\omega\:}_{d}{L}_{ir}/{r}_{\text{eq\:}}\right)\). Further, the relationship between \(\:{i}_{Lir\text{\:max\:}}\) and \(\:{L}_{ir}\) is depicted in Fig. 5, which serves as a guideline for appropriately choosing the inductance value as desired.

Soft-charging inductor values versus impulsive current.

Power converters experience two primary types of power losses: (i) switching losses (PSw) and (ii) conduction losses (PCon). Switching losses are determined by factors such as the voltage stress on the device, the current flowing through it, and the frequency of switching actions (the number of times the device turns ON and OFF). These losses occur during the transitions between the ON and OFF states of the switches, where energy is dissipated due to the inherent characteristics of the semiconductor devices. However, it is important to note that switching losses in most power converter designs are generally minimal when compared to conduction losses. Conduction losses arise when the device is in its ON state, where current flows through the switches and diodes, leading to power dissipation due to their internal resistance. These losses can significantly impact the overall efficiency of the converter, especially at higher load levels. The switching and conduction loss expressions are given below:

where the switching loss is expressed using the following expression:

The conduction loss is broadly dependent on the on-state resistance and RMS current across the switches (PCon, SW) and diodes (PCon, D) during the conduction period and is expressed as given in (23).

where Ron denotes the on-state resistance, IF_rms denotes the forward current, and VF denotes the forward voltage drop. Thus:

Therefore, the total conduction loss of the switch (PCon_Sw) is expressed as:

Also, one can express the following:

Finally, the total conduction loss (PCon_D) is given as:

Table 3 comprehensively compares the proposed topology and existing designs in the field.

Notably, the topologies in7,8 lack voltage-boosting capabilities. Their operational principles closely resemble the flying capacitor concept; however, they do not incorporate soft-charging inductors to limit inrush current. Instead, these topologies rely on separate algorithms or sensors to manage the voltages across the flying capacitors, adding complexity to their implementation. In contrast, the topologies presented in10,11 demonstrate higher voltage-boosting capabilities, achieving output voltages four times greater than the input voltage while maintaining a lower device count. Despite these advantages, they have several drawbacks: they lack mid-point connection features, necessitate higher voltage ratings for the switched capacitors (up to eight times that of the proposed topology), and have maximum blocking voltages equal to the output voltage. These factors contribute to increased costs and higher power losses. The ANPC inverter topologies discussed in9,12,13,15,16 include the beneficial mid-point connection feature, which allows for extension to three-phase systems. Although the designs in9,15 appear similar to the proposed topology, the latter stands out due to its reduced total component count and effective suppression of inrush current. While topology16 offers a higher voltage gain than the proposed design, it employs three switched capacitors, each with voltage ratings that exceed those of the proposed topology. This increases the system’s complexity and cost. Hence, the proposed topology enhances performance through its innovative design and addresses the limitations present in existing configurations.

Simulations using MATLAB/Simulink software were conducted to evaluate the proposed topology’s performance under various dynamic conditions, such as changes in load. These simulations provide valuable insights into how the inverter responds to fluctuations in operational parameters. The parameters and specifications for both the simulation and experimental setups are detailed in Table 4. The input voltage is maintained at 200 V, with the DC-link voltage set at 100 V, utilizing two sources (Vdc1 and Vdc2) for effective voltage management. This configuration employs a DC-link capacitor rated at 100 V and 470 µF to ensure stability and reliable operation.

Due to the non-continuous charging nature of the SCs, the voltage rating and capacitance values are set at 50 V and 2.7 mF, respectively, which are higher than those of the DC-link capacitors. The proposed topology is initially tested with a resistive load of R = 80 Ω. In this configuration, the absence of a load inductor results in a significant inrush current, as depicted in Fig. 6.

Simulation results: (a) output voltage (vo), (b) output current (io), (c) dc-link voltage, (d) dc-link current, (e) switched capacitor voltage, (f) switched capacitor currents, (g) VS1-switch voltage, (h) iS1-switch current, (i) VS7-switch voltage, and (j) iS7-switch current.

When the pure resistive load is connected, the system operates at a maximum switching frequency of 5 kHz, allowing observation of the output voltage and current. Subsequently, the load is switched to a combination of resistive and inductive components, specifically 50Ω/100mH. This combination leads to a maximum load current of 3.3 A, as illustrated in Fig. 6b. The corresponding output voltage remains stable even at a maximum lagging power factor of 0.85. Figure 6c through 6f record the voltages and currents across the DC-link and switched capacitors during the load transitions. Additionally, the switch voltage and current are monitored under resistive and resistive-inductive load conditions, as shown in Fig. 6g through 6j. Specifically, switch S₁ experiences a peak current of approximately 15 A when under the RL load, primarily due to the charging of the SCs. Furthermore, the voltages and currents for the load-side switch S₇ are captured, with a maximum value of 3.3 A, equal to the load current. Notably, the inrush current observed is four times greater than the load current, indicating a significant surge during startup. Since the proposed topology is a family of the ANPC structure, it can be used for any application under the ANPC. Further, the proposed topology is validated in simulation under non-linear loading conditions such as pure inductive and rectifier load. The single-phase full-bridge rectifier is used at the load of the proposed inverter, i.e., the inverter output voltage (Vinv) is fed to the input of the rectifier, and the results are captured as shown in Fig. 7a-f. Figure 7a, b is the inverter output voltage and current, and Fig. 7c, d is the rectifier output voltage and current for R = 50 Ω. Further, the switched capacitor voltages are also shown to confirm the reliable operation of the proposed topology under non-linear loading conditions.

Simulation results of rectifier load for R = 50 Ω: (a) inverter output voltage, (b) inverter output current, (c, d) rectifier voltage and current, respectively, (e–f) switched capacitor voltages during the rectifier load.

Simulation results of pure inductive load at L = 50mH, (a) load voltage, (b) load current, and (c, d) switched capacitor voltages.

As shown in Fig. 8a-d, the proposed topology is simulated under a purely inductive load, i.e., L = 50 mH, which gives a 90o phase-shifted current. It is also clear that the proposed topology can operate under highly inductive loading conditions, i.e., it is suitable for motoring applications such as water pumping, AC drives, etc. In addition to this, the proposed topology can be integrated with fuel cells for grid-tied applications. Since the proposed topology has boosting ability, the front DC/DC converter size will be reduced compared to existing topologies. Also, mid-clamping is an additional feature of the proposed topology compared to the one presented in31; due to this mid-point clamping, the proposed topology can be easily extended to a three-phase system.

Figure 9a and b denote the total harmonic distortions of the proposed topology for fsw= 5 kHz. The proposed modulation scheme and topology combination produce low voltage THD, 11.96% for voltage and 0.56% for current under the load value of R = 50Ω, L = 100mH. However, this THD can be further minimized by increasing the switching frequency, but it may affect efficiency and increase the temperature of the switches.

Simulation results of total harmonic distortion for R = 50Ω and L = 100mH: (a) Voltage, and (b) Current.

Table 5 summarizes the voltage and maximum current flowing through the individual switches, confirming that the proposed topology includes four switches experiencing high inrush currents and two switches subjected to high voltage stress, where the maximum blocking voltage equals the input voltage. However, most switches experience reduced voltage stress, rated at half of the input voltage. This design feature effectively minimizes the overall voltage stress on the topology, enhancing its reliability and performance in practical applications.

Figure 10 shows the prototype setup photo. In this experiment setup, the MOSFET switches STB57N65M5 650 V/42A, TLP 250 gate driver circuits, and toroidal core inrush current limit inductor with a maximum of 33µH are used. Further, the DC-link capacitors ERHA651LGC222MDH0M/650V- Chemi-Con and for SCs B41607A0118M002 from TDK is used. Moreover, other measuring instruments such as voltage, current, and waveform capture DSO are from Keysight products. TMS320F28379d microcontroller is used to produce the required switch pulses. The rheostat and multiple tap inductor varying from 10mH-100mH type inductor is used at the load.

Hardware photo of the topology investigated in this work.

The performance of the proposed topology has been rigorously validated using simulation tools, demonstrating enhanced performance during load changes. The analysis includes a discussion of the maximum currents through the switches and capacitors, highlighting a significantly lower inrush current than existing topologies reported in the literature. However, it is essential to verify these findings through experimental testing to confirm the superiority and practical feasibility of the proposed design. As depicted in Fig. 11a,b and 12a–c, experimental results for the proposed topology were obtained under various testing conditions. Consistent with the simulation parameters, the input voltage is set at 200 V, with load configurations of 80 Ω for purely resistive loads and 50 Ω in combination with a 100 mH inductor for resistive-inductive loads. These loads were implemented using rheostats and variable inductors, capable of handling a maximum current of 20 A.

Initially, the DC-link capacitors are pre-charged, while the switched capacitors remain un-charged. To effectively manage inrush current during startup conditions, a small inductor rated at 33 µH is utilized as an inrush current limiter. This design choice is critical in mitigating the initial current surge, protecting the circuit components, and ensuring stable operation.

The experimental results complement the simulation findings, providing robust evidence of the proposed topology’s effectiveness and reliability across various operational scenarios. This comprehensive approach underscores the topology’s potential for application in diverse fields, particularly in systems requiring efficient and stable power conversion. The output voltage and current were captured using a Keysight MSOX3104A oscilloscope, which features a bandwidth of 1 GHz and four channels.

Case I: For resistive and inductive load.

During testing with a purely resistive load, i.e., R = 80 Ω, as shown in Fig. 11a, a maximum load current of 2.5 A was observed. The switched capacitor voltages (VSC1-2) are also shown in Fig. 11a, and they maintain the SC voltage at 50 V. Further, to validate the performance of the proposed topology under the lagging power factor, the load was subsequently switched to a combination of resistive and inductive elements, i.e., the inductor is included at the load along with the resistor (R = 50 Ω & L = 100 mH). These findings confirm that the proposed topology performs effectively under unity and lagging PF conditions (0.85), as shown in Fig. 11b). This is clear evidence that the proposed topology can be operated under varying power factors and confirms that the SC voltage is maintained even when the load suddenly changes. Since the proposed topology ensures that each capacitor is charged and discharged equally for every fundamental cycle, capacitor mismatching or unbalancing is impossible because the SCs are parallel to the DC-link capacitors. However, there is a possibility of lowering the voltage across the SCs due to degradation or lifetime reduction. In such a case, the SCs can replace or implement fault-tolerant techniques to mitigate voltage unbalancing.

Experimental results: (a) R-load output voltage and current, and (b) RL-load output voltage and current.

Case II: Dynamic performance validations.

The input voltage can fluctuate significantly in many single-phase inverter applications, such as rooftop photovoltaic (PV) systems. Therefore, validating inverter performance under sudden step input changes is essential. This testing was applied to the proposed topology to evaluate its response, as illustrated in Fig. 12a. The topology demonstrates exceptional suitability for applications involving rapid changes in input conditions, particularly in renewable energy sources. Moreover, many industrial and household appliances operate under dynamic loads that vary throughout their operational periods. Consequently, inverters must be designed to respond effectively to these dynamic load changes, which is a critical consideration when developing a robust inverter system. To assess this capability, the proposed topology was tested by continuously varying the load between RL and purely R configurations, with results presented in Fig. 12b. This testing further validates the topology’s ability to handle linear and nonlinear load variations. Finally, the modulation index (D) is another vital factor for inverters, as it must be adjusted to maintain the load voltage according to shifting load requirements. In this research, the modulation index was varied by up to 50%, and the corresponding experimental waveform is depicted in Fig. 12c. The discussions and experimental waveforms captured throughout this testing confirm that the proposed topology excels under various loading conditions, demonstrating its ability to boost voltage and adapt effectively to dynamic operational demands. This robustness positions the topology as a promising candidate for modern inverter applications in diverse fields.

Experimental results: (a) step-input change, (b) step changes in load, and (c) variation of the modulation index: 50% and 80%.

The proposed topology’s power loss and efficiency have been thoroughly evaluated using PLECS software, with results illustrated in Fig. 13a, b. The analysis focuses on individual components, specifically the switches and diodes, under a load of 250 W for a purely resistive configuration. To assess the performance, both Psw​ and PCon were analyzed with a load value of 80 Ω. The maximum conduction losses were observed in switches S₁, S₂, S₇, and S₈, primarily due to their continuous operation during the waveform’s positive and negative half cycles.

Power loss and efficiency analysis: (a) Simulation results of switching and conduction loss, and (b) Output power vs. efficiency.

Efficiency calculations for the proposed topology were conducted using PLECS simulations and corroborated by experimental measurements, as shown in Fig. 13b. The results reveal a maximum efficiency of 98.4% during simulations and approximately 97% in experimental conditions at 100 W. This high efficiency is impressively maintained up to 250 W, with negligible variations, underscoring the robustness of the design. These findings not only highlight the low power loss characteristics of the proposed topology but also confirm its effectiveness in maximizing efficiency across a range of operating conditions. This combination of simulation and experimental validation reinforces the topology’s potential for practical applications, making it a compelling choice for modern power conversion systems.

A novel 9 L boost-type ANPC inverter topology is presented, supported by comprehensive simulation and experimental results derived from prototype testing. This innovative topology not only showcases the fundamental principles of the switched capacitor concept but also elucidates its operational modes in detail. The analysis covers both dynamic and steady-state performance, providing a thorough discussion of the results obtained. The validation of the proposed topology under non-linear loads, including rectifiers and purely inductive configurations, demonstrates its versatility and effectiveness. To highlight the superiority of the proposed modulation technique, it is compared with existing conventional modulation schemes. The voltage and current THD of the proposed topology are measured and plotted, revealing significant improvements. Comparative evaluations reveal that the proposed topology features fewer switches and lower voltage stress on its components and devices. This design optimization confirms a substantial reduction in overall costs, enhancing economic viability. Moreover, the proposed topology is well-suited for various applications, including rooftop photovoltaic systems and fuel cell integrated grid systems. Its efficiency and reliability position it as a leading choice in modern power conversion technologies, paving the way for advancements in renewable energy integration and other high-performance scenarios.

Future work will focus on several key areas to enhance the proposed topology’s capabilities and applications, such as the development and implementation of advanced control algorithms to optimize performance in real-time applications, particularly under varying load conditions, exploring the integration of the proposed inverter with energy storage systems, such as batteries and supercapacitors, to improve grid stability and energy management, while paying special attention further research into harmonic mitigation techniques to improve the quality of output voltage and current, enhancing overall system performance. Addressing these areas will allow the proposed ANPC inverter topology to be further optimized and adapted for a wide range of applications, contributing to the advancement of power conversion technologies.

Data Availability StatementDue to their large size, the datasets generated during the current study are not publicly available but are available from the corresponding author upon reasonable request.

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Department of Electrical and Electronics Engineering, Faculty of Engineering and Computer Science, Jazan University, Jizan, 45142, Saudi Arabia

Zuhair Alaas

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Z.A., prepared this article to present a comprehensive numerical result set that aligns with developed theoretical and experimental findings. Developed a novel Active Neutral Point Clamped (ANPC) based nine-level inverter topology that features low-energy storage switched capacitors, significantly enhancing efficiency and reducing the number of devices required. Dynamic load management: Showcased the inverter’s ability to function efficiently under varying load conditions, making it suitable for various power electronics applications. In-depth analysis: Thorough investigations into inrush current limiting techniques and switched capacitor mechanisms addressed prevalent challenges in multilevel inverter design. Validated the proposed topology’s performance through extensive MATLAB/Simulink simulations and prototype hardware testing, demonstrating its feasibility and advantages over existing designs. Cost-effectiveness: The decreased overall component count and energy storage needs result in a more economical solution for high-performance inverter applications. Performance optimization: Enhanced system efficiency by integrating low-energy storage switched capacitors, leading to better energy management and decreased operational losses. Harmonic distortion reduction: An enhanced modulation scheme has been introduced to minimize total harmonic distortion, resulting in a higher-quality output waveform.

Correspondence to Zuhair Alaas.

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Alaas, Z. A new active neutral point clamped (ANPC) nine-level inverter topology with low energy storage switched capacitors. Sci Rep 15, 7031 (2025). https://doi.org/10.1038/s41598-025-87302-2

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Received: 01 December 2024

Accepted: 17 January 2025

Published: 27 February 2025

DOI: https://doi.org/10.1038/s41598-025-87302-2

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